In deep submicron processes, the issue of achieving reasonable yield in light of manufacturing variability is a considerable challenge. At approximately the 130 nm process node, the underlying physics and quantum mechanical effects begin to govern the behavior of CMOS technology and the ability to dictate and predict the desired behavior begins to decline. In such technologies, for example, channel dopants are in concentrations on the order of fewer than 100 atoms with uncontrollable fluctuations from one device to another; line-width Cd-Variation becomes difficult or nearly impossible to control despite recent advances in lithography techniques; leakage becomes extreme; and electrons exhibit direct tunneling through dielectrics almost as if the dielectrics were not present. In addition to these limitations of solid state device physics, manufacturing technologists face other difficulties in fabricating circuit structures, such as ultra-deep ultra-violet lithography, optical phase correction (OPC), stepper control, phase shift masks (PSM), chemical mechanical polishing (CMP), depth of field correction (DOF), immersion lithography, etc.
These issues manifest uncertainty, variation, and great difficulty in controlling and managing manufacturing processes, which can result in tremendous yield loss. One traditional approach includes implementing Monte Carlo based simulation to model and predict yields, and then to make changes to improve yield. This approach can provide reasonable results for smaller circuits and small numbers of varying design metrics, but they may be unable to practically provide meaningful results in context of entire, typically larger and more complex, semiconductor devices having many associated design variables. Another traditional approach seeks to address these limitations by deriving “general-purpose” process corners at which to simulate a design-for-yield analysis and/or prediction. These general-purpose process corners are often non-physical and/or unrealistic, and may not explore sensitivities that can be critical to metrics of concern for a given circuit or circuit path.
Each circuit and each circuit metric may have its own sensitivities to process, temperature, voltage, signal and other environmental conditions. If these sensitivities all align, they can be systematically offset to improve yield. If not, achieving a reasonable yield can force appreciable trade-offs, which can become so severe as to produce a non-overlapping zero-yielding solution (e.g. when manufacturing engineers try to improve the yield by shifting the process, they can improve a Circuit A at the cost of hindering a Circuit B). For example, there may be a process condition at which a data path of a microprocessor will yield well, but a Level 2 Cache in the same microprocessor will not. As the process is offset or shifted to accommodate the Level 2 Cache yield, the data path yield may start to decline. Therefore, satisfying a wafer's parametric yield does not necessarily mean that all the circuits contained on the wafer will likewise have satisfactory yield. Typically, a product is considered well-yielding only when all probed parametric measurements and behavior characteristics simultaneously yield well.